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Integrated Circuit Systems, Inc.
ICS9248-168
AMD - K7TM Clock Generator for Mobile System
Recommended Application: VIA KT133 style chipset Output Features: * 1 - Differential pair open drain CPU clocks * 1 - CPU clock @ 3.3V * 7 - SDRAM @ 3.3V * 8 - PCI @ 3.3V, * 1 - 48MHz, @ 3.3V fixed. * 1 - 24/48MHz @ 3.3V * 3 - REF @ 3.3V, 14.318MHz. Features: * Up to 153MHz frequency support * Support power management: CPU stop and Power down Mode from I2C programming. * Spread spectrum for EMI control ( 0.25% to 0.6% center, or 0 to -0.5% or -1.0% down spread). * Uses external 14.318MHz crystal
Pin Configuration
VDDREF X1 X2 *FS2/PCICLK_F *FS1/PCICLK0 VDDPCI GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 GND VDDPCI PCICLK6 *SDRAM_STOP# *PCI_STOP# BUFFER_IN AVDD GND GND *FS0/48MHZ *SEL24_48#/24_48MHz VDD48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0 REF1 REF2 GND GND VDD 2 CPUCLK 2 CPUCLKT0 2 CPUCLKC0 CPU_STOP#* PD#* SDRAM0 SDRAM1 VDDSDR GND SDRAM2 SDRAM3 GND VDDSDR SDRAM4 SDRAM5 SDRAM_F SCLK SDATA
1
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD 1 These outputs have double strength to drive 2 loads. 2 These outputs can be set to 1.5X strength through I2C
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz REF (2:0) CPUCLK
CPU DIVDER Stop
Functionality
FS2 0 0 0 0 1 1 1
CPUCLKT0
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
CPU 100.00 133.33 100.00 133.33 100.00 133.33 90.00 120.00
PCI 33.33 33.33 33.33 33.33 33.33 33.33 30.00 30.00
ICS9248-168
S p re a d Pe rc e n t a g e +/- 0.35% Center Spread +/- 0.35% Center Spread 0 to - 0.5% Down Spread 0 to - 0.5% Down Spread +/- 0.6% Center Spread +/- 0.6% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread
CPUCLKC0
1
SEL24_48# SDATA SCLK FS (2:0) PD# CPU_STOP# PCI_STOP# SDRAM_STOP# BUFFER_IN
Control Logic
PCI DIVDER
Stop
PCICLK (6:0) PCICLK_F
SDRAM DRIVER
Stop
SDRAM (5:0) SDRAM_F
Config. Reg.
9248-168 Rev B 01/09/01
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ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-168
Pin Descriptions
PIN NUMBER 1, 6, 14, 24, 30, 35, 43 2 3 4
P I N NA M E VDD X1 X2 FS21, 2 PCICLK_F FS1 PCICLK0 GND PCICLK (6:1) SDRAM_STOP# PCICLK_STOP# BUFFER IN AVDD FS01, 2 48MHz SEL24_48#1, 2 24_48MHz SDATA SCLK SDRAM_F
1, 2
TYPE PWR IN OUT IN OUT IN OUT PWR OUT IN IN IN PWR IN OUT IN OUT I/O IN OUT OUT IN IN OUT OUT OUT OUT
DESCRIPTION Power supply, nominal 3.3V Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (36pF) Frequency select pin. Latched Input. Internal Pull-up to VDD Free running PCI clock not affected by PCI_STOP# for power management. Frequency select pin. Latched Input. Internal Pull-up to VDD PCI clock output Ground PCI clock outputs. Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input low Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low Input to Fanout Buffers for SDRAM outputs. Supply for core, & CPU 3.3V Frequency select pin. Latched Input 48MHz output clock Logic input to select 24 or 48MHz for pin 25 output 24MHz/48MHz clock output Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant Free running SDRAM clock not affected by SDRAM_STOP# for power management. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Powers down chip, active low This asynchronous input halts CPUCLKT, CPUCLKC & SDRAM at logic "0" level when driven low. "Complementory" clock of differential pair CPU output. This open drain outputs needs an external 1.5V pull-up. "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. 3.3V CPU clock output powered by VDDA 14.318 Mhz reference clock.
5 7, 13, 20, 21, 31, 34, 44, 45 15, 12, 11, 10, 9, 8
16 17
18 19 22 23 25
26
27
28, 29, 32, 33, 36, 37 SDRAM (5:0) 38 39 40 41 42 46, 47, 48
PD# CPU_STOP#1, CPUCLKC0 CPUCLKT0 CPUCLK REF0 (2:0)
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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2
ICS9248-168
General Description
The ICS9248-168 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides all clocks required for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-168 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDD48 = 48MHz, Fixed PLL VDDA = VDD for Core PLL VDDREF = REF, Xtal
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3
ICS9248-168
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2, Bit 7:4
Bit 3 Bit 1 Bit 0
Description Bit Bit Bit Bit Bit CPUCLK PCICLK 2 7 6 5 4 (MHz) (MHz) 0 0 0 0 0 100.00 33.33 0 0 0 0 1 133.33 33.33 0 0 0 1 0 100.00 33.33 0 0 0 1 1 133.33 33.33 0 0 1 0 0 100.00 33.33 0 0 1 0 1 133.33 33.33 0 0 1 1 0 90.00 30.00 0 0 1 1 1 120.00 30.00 0 1 0 0 0 100.30 33.43 0 1 0 0 1 133.73 33.43 0 1 0 1 0 100.30 33.43 0 1 0 1 1 133.73 33.43 0 1 1 0 0 101.00 33.67 0 1 1 0 1 134.66 33.67 0 1 1 1 0 102.00 34.00 0 1 1 1 1 136.00 34.00 1 0 0 0 0 103.00 34.33 1 0 0 0 1 137.33 34.33 1 0 0 1 0 104.00 34.67 1 0 0 1 1 138.66 34.67 1 0 1 0 0 105.00 35.00 1 0 1 0 1 140.00 35.00 1 0 1 1 0 107.00 35.67 1 0 1 1 1 142.66 35.67 1 1 0 0 0 110.00 36.67 1 1 0 0 1 146.66 36.67 1 1 0 1 0 115.00 38.33 1 1 0 1 1 153.33 38.33 1 1 1 0 0 100.00 33.33 1 1 1 0 1 133.33 33.33 1 1 1 1 0 100.00 33.33 1 1 1 1 1 133.33 33.33 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0.25% Center Spread 0 - Running 1- Tristate all outputs
PWD Spread Precentage +/- 0.35% Center Spread +/- 0.35% Center Spread 0 to - 0.5% Down Spread 0 to - 0.5% Down Spread +/- 0.6% Center Spread +/- 0.6% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.60% Center Spread +/- 0.60% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.35% Center Spread +/- 0.50% Center Spread +/- 0.50% Center Spread 0 to -1.0% Down Spread 0 to -1.0% Down Spread
Reserved 00101
0 1 0
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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4
ICS9248-168
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
22 5 4 42 41, 40 42
PWD
1 1 1 1 1 1 1 1 FS0 FS1 FS2
DESCRIPTION
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
4 15 12 11 10 9 8 5
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
PCICLK_F PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
CPUCLK 0=1.5X 1=1X Reserved CPUCLKT/C 0=1.5X 1=1X Reserved CPUCLK
Byte 3: Active/Inactive Register (1= enable, 0 = disable)
Byte 4: SDRAM , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
23 22 23 48 47 46 -
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
Reserved SEL24_48# 48MHz 24_48MHz REF0 REF1 REF2 Reserved
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
27 28 29 32 33 36 37 1 1 1 1 1 1 1 1
DESCRIPTION
Reserved SDRAM_F SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
PIN# PWD
1 1 1 1 1 1 1 1
DESCRIPTION
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
0 0 0 0 0 1 1 0
DESCRIPTION
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note: Don't write into this register, writing into this register can cause malfunction
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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5
ICS9248-168
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors Operating Supply Current IDD3.3OP C L =20 pF; SDRAM not running Power Down PD Input frequency Fi VDD = 3.3 V Input Capacitance1 Clk Stabilization 1 Skew window1
1
MIN 2 VSS-0.3 -5 -200
12 27
MAX UNITS VDD+0.3 V 0.8 V 5 uA uA uA 75 180 mA 280 600 uA 14.318 16 MHz 5 45 3 250 500 pF pF ms ps
TYP
From VDD = 3.3 V to 1% target Freq. TCPU-PCI window Vt=50% CPU - 1.5V PCI; CPU Leads
C IN C INX TSTAB
Logic Inputs X1 & X2 pins
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER Output Impedance
1 1
SYMBOL RDSP5B RDSN5B VOH5 VOL5 IOH5 IOL5
1 tr5 1 tf5 1 dt5 1 1 tjcyc-cyc5
CONDITIONS VO=VDD*(0.5) VO=VDD*(0.5) IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 20 20 2.4
TYP 24 44
MAX UNITS 60 60 0.4 -22 V V mA mA ns ns % ps
Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
16 1.7 1.5 45 52.8 770 4.0 4.0 55 1000
Duty Cycle
1
Jitter, Cycle-to-Cycle
Guaranteed by design, not 100% tested in production.
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6
ICS9248-168
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Output Low Current Output Low Current Rise Time 1 Fall Time 1 Duty Cycle Skew window
1 1 1
SYMBOL VOH2B VOL2B IOL2B IOL2B tr2B 1 tf2B 1 dt2B
1 tsk2B 1 tjcyc-cyc2B 1 tjabs2B 1
CONDITIONS IOH = -12.0 mA IOH = 12.0 mA VOL = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOL = 2.0V VOH = 2.0 V, VOL = 0.4V VT = 1.5V VT = 1.5V VT = 1.5V VT = 1.5V
MIN 1 18 18
TYP
MAX 1.8 0.8
0.9 0.8 45 51.5 125
1.6 1.6 55 200 300 250
UNITS V V mA mA ns ns % ps ps ps
Jitter, Cycle-to-cycle Jitter, Absolute
1
Notes: 1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output Low Current Rise Time 1 Fall Time 1 Differential voltage-AC Differential voltage-DC Diff Crossover Voltage Duty Cycle
1 1 1 1 1 1
SYMBOL
1 ZO
CONDITIONS VO=VX Termination to Vpull-up(external) Termination to Vpull-up(external) VOL = 0.3 V VOH = 1.2 V, VOL = 0.3V VOL = 0.3 V, VOH = 1.2V Note 2 Note 2 Note 3 VT = 50% VT = 50% VT = VX VT = 50%
MIN 1 18
TYP
MAX 60 1.8 0.8
UNITS V V mA ns ns V V V % ps ps ps
VOH2B VOL2B IOL2B
1 tr2B 1 tf2B
0.5 0.3 0.4 0.2 1.2 45 0.82 51.5 125
0.9 0.9 Vpull-up(ext) + 0.6 Vpull-up(ext) + 0.6 1.8 55 200 300 250
VDIF VDIF VX
1 dt2B 1 tsk2B 1 tjcyc-cyc2B 1 tjabs2B
Skew window
Jitter, Cycle-to-cycle Jitter, Absolute
1
Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input Level and VCP is the "complement" input level. 3 - Vpull-up(external) = 2.7V, Min=Vpull-up(external)/2-150mV; Max=Vpull-up(external)/2 +150mV
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7
ICS9248-168
Electrical Characteristics - SDRAM_OUT
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER Output Impedance Output Impedance
1 1
SYMBOL RDSP3 RDSN3 VOH3 VOL3 IOH3 IOL3
1 tr3 1 tf3 1 dt3 1 1
CONDITIONS VO=VDD*(0.5) VO=VDD*(0.5) IOH = -11 mA IOL = 11 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2
TYP 11 12
MAX UNITS 24 24 0.4 -12 V V mA mA ns ns % ps ns
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
12 0.9 0.8 45 51.5 220 3 1.5 1.5 55 250
Duty Cycle
Skew (ouput to output)
1
tsk3A tsk3B
Skew (Buffer In to output)
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL
1 RDSP2B 1 RDSN2B
CONDITIONS VO=VDD*(0.5) VO=VDD*(0.5) IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 12 2.6
TYP 24 23
MAX UNITS 55 55 0.4 -16 V V mA mA ns ns % ps ps
VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tjcyc-cyc1
19 1.29 1.29 45 50.2 280 86 2.5 2.5 55 400 200
Duty Cycle
Skew window Jitter, Cyc-to-Cyc
1
Guaranteed by design, not 100% tested in production.
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8
ICS9248-168
Electrical Characteristics - PCICLK_F
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER Output Impedance Output Impedance
1 1
SYMBOL RDSP1B RDSN1B VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 VO=VDD*(0.5) VO=VDD*(0.5) IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V
CONDITIONS
MIN 12 12 2.6
TYP 14 13
MAX UNITS 55 55 0.4 -12 V V mA mA ns ns % ps ps
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1 1
12 1.4 1.3 45 50.2 280 2.0 2.0 55 400 200
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Duty Cycle
Skew window
1
tsk1 tjcyc-cyc1
Jitter, Cycle-to-Cycle
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER Output Impedance Output Impedance
1 1
SYMBOL RDSP5B RDSN5B VOH5 VOL5 IOH5 IOL5
1 tr5 1 tf5 1 dt5 1
CONDITIONS VO=VDD*(0.5) VO=VDD*(0.5) IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V 24 48 MHz
MIN 20 20 2.4
TYP 24 44
MAX UNITS 60 60 0.4 -22 V V mA mA ns ns % ps
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
16 1.8 1.8 45 53 150 4.0 4.0 55 500
Duty Cycle
1
Jitter, Cycle-to-Cycle
tjcyc-cyc5
1
VT = 1.5 V
Guaranteed by design, not 100% tested in production.
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9
ICS9248-168
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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10
ICS9248-168
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248168 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Fig. 1
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11
ICS9248-168
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. CPU_STOP# is considered to be a don't care during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT CPUCLKC
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-168 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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12
ICS9248-168
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-168. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-168. 3. All other clocks continue to run undisturbed.
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13
ICS9248-168
SYMBOL
In Millimeters COMMON DIMENSIONS MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MAX .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 28 34 48 56 64
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MAX 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inch) MAX .380 .455 .630 .730 .830
Ordering Information
ICS9248yF-168-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
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ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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Price & Availability of ICS9248-168

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